A "Zero-Time" VLSI Sorter

A hardware sorter suitable for VLSI implementation is proposed. I t operates in a parallel and pipelined fashion, with the actual sorting time absorbed by the inputloutput time. A detailed VLSI implementation is described which has a very favorable device count compared to existing static RAM. 1. Introduction Sorting is one of the most important operations in data while the item at the top cell goes out of the array in 'an processing. It is estimated that in data processing centers upward data flow.) The initial sequence is entered into the over 25 percent of CPU time is devoted to sorting [I]. Many sorter one item at each step. After the last item has been sequential and parallel sorting algorithms have been pro-entered, the data flow direction is reversed, and the sorted posed and studied [2-131. Implementation of various sorting sequence is then extracted as output, also serially. Each step, algorithms in different hardware structures has also been executed synchronously and simultaneously by all the cells,